1. Field of the Invention
Embodiments of the present disclosure relate to display technology, and more particularly to a testing circuit of the liquid crystal display (LCD) and the testing method thereof.
2. Discussion of the Related Art
In the LCD manufacturing process, display panels are tested before being mounted with the chip on film (COF) and the PCB. The testing, which are classified according to the probes, includes full contact mode, shorting bar mode, and one gate one date mode.
In the full contact mode, the number of the pins on the probe is basically the same with that of the pins within the terminal area of the display panel, which is of the range between one thousand to several thousands. The electrical waveforms used by the pins are from the generator that is the same with the module PCB. Thus, this testing method is reliable for detecting Mura, defective dots, and defective lines. Also, many detecting frames can also be displayed. However, the probe is expensive and fragile. In addition, the alignment between the probe and the display panel is critical and thus the efficiency is low.
In the shorting bar mode, the pins of the gate terminals are connected to form a short circuit. Generally, the gate terminals in odd rows are connected to form a first testing pad, and the gate terminals in even rows are connected to form a second testing pad. One short connection is established by the data lines coupled with the red sub-pixels to form a third testing pad. Similarly, short connections are between the data lines coupled with the green sub-pixels and the data lines coupled with the blue sub-pixels to form a fourth testing pad and a fifth testing pad. It can be seen that the number of the gate terminals has been decreased, and thus the cost of the probe is low. In addition, the dimension of the testing pad is greatly larger than that of the terminals of the probe. Thus, it is easy to align the probe with the display panel so that the manufacturing efficiency is enhanced. However, only specific frames can be displayed, and the signals provided by the probe is much different from that provided by the module PCB, which causes the testing unreliable.
In the one gate one date mode, after the probe is pressed on the terminal area of the display panel by conductive tape or adhesive, the short connections are between all of the scanning lines, and also between the data lines. The display panel is treated as a sub-pixel with such configuration. The cost of this mode is between the above-mentioned modes. Generally, the one gate one date mode is adopted to be one supplementary detecting method after the shorting bar mode as the fewest frames can be displayed and the precision is low.
Color shift effect is a critical issue for vertical alignment (VA) mode LCDs. A plurality of solutions, such as coupling capacitor (CC) method, dual TFT driving method (TT), and charge sharing method, are provided. For the above modes, one sub-pixel is divided into a main area and a sub area larger than the main area, and this configuration is usually referred to as “8 domain” design.
Within the configuration, each sub-pixel is driven by dual gate lines, including a charging gate line and a sharing gate line as shown in FIG. 1. The gate of the transistors T1, T2 couple to the charging gate line, the source of the transistors T1, T2 couple to the data line D, and the drain of the transistors T1, T2 respectively couple to the electrodes in the main area and the sub area. The gate, source, and drain respectively couple to the sharing gate line, the source of the transistor T2, and one end of the capacitor (Cdown). Another end of the capacitor (Cdown) couples to a shared voltage (Vcom).
The sub-pixel in FIG. 1 may be the red, green, or blue sub-pixel. The pixels formed by the red, the green, and the blue sub-pixel are arranged in a matrix on the display panel. The matrix includes sub-pixel rows and sub-pixel columns The short connection is between the sharing gate line coupled with the m-th sub-pixel row and the charging gate line coupled with the (m+2n)-th sub-pixel row, and the m and n are positive integers.
When performing the testing with the shorting bar mode, the charging gate lines coupling with the odd sub-pixel row form the short connection, and the charging gate lines couple to the first gate testing pad. The charging gate lines coupling with the even sub-pixel row form the short connection, and the charging gate lines couple to the second gate testing pad. As such, the charging gate line and the sharing gate line of the sub-pixels of the same row are at a low voltage level or at a high voltage level at the same time. However, there is a time gap between the turn-on time of the transistor T3 and that of the transistors T1, T2. The defective dots cannot be detected within the time gap. It is to be noted that the defective dots includes dead dot, bright dot, and dark dot. The dead dot relates to a black dot in a white frame or a white dot in a black frame. The black dot relates to a red, green or blue dot in the black frame. The dark dot relates to a dot that is not purely red, green, or blue in the white frame. The number of defective dots is a key factor for evaluating the display performance of the display panel.